This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
At high core voltages, there can be write failures due to false read when a timing mismatch takes place between row select and column select lines especially at skewed corners where VDDC>>VDDP. During a write to an opposite state, a write transistor in a local bit selector can pull down on a local bit line, while a memory cell pulls down on an opposite local bit line. This can result in both local bit lines being pulled down to ground, thereby likely inhibiting the memory cell from writing, resulting in write failure.